Single polysilicon layer transistor with reduced emitter and bas

Details Single polysilicon layer transistor with reduced emitter and bas Single polysilicon layer transistor with reduced emitter and bas

1988-06-29

1990-12-25

James, Andrew J.

357 59, H01L 2972

Patent

active

049807382

ABSTRACT:
A single layer polysilicon self-aligned transistor (52) is provided having a substantially vertical emitter contact region (62), such that the emitter contact region (62) does not require extending portions overlying the base region (60). Heavily doped silicided regions (68) are disposed adjacent the emitter (64) in a self-aligned process such that the base resistance of the device is minimized. A planar oxide layer (72) is formed such that the emitter contact region (62) are exposed without exposing other polysilicon gates of the integrated circuit. A metal layer (76) may be disposed over the planar oxide layer (72) to form a level of interconnects.

REFERENCES:
patent: 4495512 (1985-01-01), Isaac et al.
patent: 4686763 (1987-08-01), Thomas et al.
patent: 4705599 (1987-11-01), Suda et al.
patent: 4728618 (1988-03-01), Hirao
patent: 4847670 (1989-07-01), Monkowski et al.
IBM Technical Disclosure Bulletin, vol. 28, #1, pp. 26-27, Jun., 1985.

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