1974-12-05
1976-11-02
Wojciechowicz, Edward J.
357 51, 357 55, 357 59, 357 90, H01L 2990, H01L 2702, H01L 2904, H01L 2906
Patent
active
039900991
ABSTRACT:
A planar TRAPATT diode includes a substrate selected from an area of a silicon wafer, a diffused region within the area, a mask of an insulating layer of SiO.sub.2, and a conductive layer of polycrystalline silicon. The silicon wafer includes a doped P region adjacent to the surface thereof and a heavily doped P.sup.+ region adjacent to the P region. The TRAPATT junction is a selected area below the surface at the interface between the diffused region, which is N.sup.+, and the P region. The polycrystalline silicon layer is the dopant source for the N.sup.+ diffused region and contacts the wafer in the selected area.
REFERENCES:
patent: 3600649 (1971-08-01), Liu et al.
patent: 3663874 (1972-05-01), Fukukawa et al.
patent: 3743967 (1973-07-01), Fitzsimmons et al.
patent: 3909119 (1975-09-01), Wolley
Duigon Ferdinand Carl
Liu Shing-Gong
Christoffersen H.
Muckelroy W. L.
RCA Corporation
Williams R. P.
Wojciechowicz Edward J.
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