Method for optimizing instruction scheduling for a processor hav

Details Method for optimizing instruction scheduling for a processor hav Method for optimizing instruction scheduling for a processor hav

1992-06-10

1993-04-13

Eng, David Y.

395375, 395700, 395800, G06F 945, G06F 9455

Patent

active

052029751

ABSTRACT:
A method for scheduling instructions for a processor having multiple functional resources wherein the reordering of the instructions is accomplished in response to a simulation of the run-time environment of the target machine. The simulation of the run-time environment of the target machine is performed at compile time after the machine instructions have been generated by a compiler, or after instruction generation by an assembler. The present invention rearranges the machine instructions for a basic block of instructions into an order that will result in the fastest execution based upon the results of the simulation of the interaction of the multiple functional resources in the target machine.

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Wei-Chung, Hsu, "Register Allocation and code Scheduling for Load/Store Architecture", thesis, Univ. of Wisc.

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