Memory having looped global data lines for propagation delay mat

Details Memory having looped global data lines for propagation delay mat Memory having looped global data lines for propagation delay mat

1994-05-02

1995-03-21

LaRoche, Eugene R.

Static information storage and retrieval

Interconnection arrangements

365 51, G11C 506

Patent

active

054002745

ABSTRACT:
A synchronous memory (50) having a looped global data line (80) reduces a difference between minimum and maximum propagation delays between different locations in a memory array (51) during a read cycle of the memory (50). The looped global data line (80) has a first portion (80') and a second portion (80"). The first portion (80') extends along an edge of the memory array (51) in a direction substantially parallel to a direction of the word lines of the array (51). Sense amplifiers (73-78) are coupled to the first portion (80') of the looped global data line (80). At one end of the array (51), the second portion (80") of the looped global data line extends back in an opposite direction to the first portion (80') and is coupled to output data circuits (84). Reducing the difference in propagation delays improves noise margins and allows increased operating speed.

REFERENCES:
patent: 4926378 (1990-05-01), Uchida et al.
patent: 5021998 (1991-06-01), Suzuki et al.

Affiliated with

Also associated with

Rating

Memory having looped global data lines for propagation delay mat does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory having looped global data lines for propagation delay mat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory having looped global data lines for propagation delay mat will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1154512