Multiple level parallel magnitude comparator

Details Multiple level parallel magnitude comparator Multiple level parallel magnitude comparator

1993-02-19

1995-03-21

Wambach, Margaret Rose

Communications: electrical

Digital comparator systems

327 64, G06F 702

Patent

active

054000076

ABSTRACT:
A magnitude comparator is modified to compare the magnitudes of two large binary values more quickly and with minimum gate delays. Bit comparators are divided into groups which generate compare output signals in parallel to one another, thereby reducing magnitude comparator delay. These compare output signals are fed into a control element which determines which compare output signal is allowed to pass through as the final compare output signal. This circuitry, along with logic circuitry which indicates whether corresponding bit values within associated groups exactly match, defines a magnitude comparator block. Multiple magnitude blocks are used to facilitate the comparison of larger binary values. Each magnitude comparator block generates a compare output signal which, in turn, is an input to a corresponding gating element. Each gating element possesses a logic input signal, derived in part from its magnitude comparator block's match logic circuitry. The gating element logic input signals ensure that only the compare output signal of the magnitude comparator block having the highest order bits with magnitude difference will be allowed to propagate through as the final compare output signal.

REFERENCES:
patent: 4163211 (1979-07-01), Miura
patent: 5130692 (1992-07-01), Ando et al.
patent: 5274835 (1993-12-01), Wakatani
Electronic Engineering, J. Daniels, "Circuits for Fast Binary Addition", vol. 62, No. 760, Apr. 1990, p. 27-28.

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