Patent
1995-08-08
1996-12-31
Harvey, Jack B.
395309, G06F 1324
Patent
active
055903380
ABSTRACT:
A combined multiprocessor interrupt controller and interprocessor communication mechanism includes a system bus, an input/output bridge element coupled to the system bus, and a system controller coupled to the system bus. The input/output bridge element includes circuitry for receiving interrupt requests, for obtaining processor-associated vectors, and for packaging obtained processor-associated vectors into interprocessor communication messages. The system controller includes circuitry for receiving and decoding interprocessor communication messages, and for providing processor-associated vectors to the associated processor.
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Gaskins Darius D.
Parks Terry J.
Dell USA L.P.
Garrana Henry N.
Harvey Jack B.
Kahler Mark P.
Turner Michelle M.
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