Clock doubler and smooth transfer circuit

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395281, G06F 104, G06F 112

Patent

active

055903169

ABSTRACT:
An apparatus is disclosed for smoothly multiplying the frequency of a computer's basic clock during a burst transfer cycle and smoothly resuming the basic clock frequency upon completing the burst transfer cycle. A fixed frequency multiplier is connected to the basic clock to generate a clock whose frequency is a multiple of the basic clock frequency. A decoder which operates synchronously with the fixed frequency multiplier clock responds to control signals of the expansion bus to detect the start and the end of a burst transfer cycle. The decoder also toggles a speed-up signal during the burst transfer cycle on the rising edges of the fixed frequency multiplier clock. The speed-up signal and the basic clock is provided to a variable frequency multiplier which multiplies the frequency of the basic clock when the speed-up signal is toggled and reproduces the frequency of the basic clock when the speed-up signal is deasserted, thus providing a clock signal whose rising edges are aligned with the rising and falling edges of the basic clock and whose frequency is a multiple of the basic clock frequency during the burst transfer cycle.

REFERENCES:
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patent: 5101492 (1992-03-01), Schultz et al.
patent: 5295247 (1994-03-01), Chang et al.
patent: 5448715 (1995-09-01), Lelm et al.
patent: 5485602 (1996-01-01), Ledbetter, Jr. et al.
EISA With Enhanced Master Burst (EMB), Addendum (Rev. 1) .COPYRGT.1993 BCPR Services, Inc.

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