Dual-port data cache memory

Details Dual-port data cache memory Dual-port data cache memory

1993-01-05

1996-12-31

Chan, Eddie P.

Static information storage and retrieval

Magnetic bubbles

Guide structure

395403, 395445, 39542101, 39542108, 39542109, 36523005, G06F 1208

Patent

active

055903070

ABSTRACT:
A dual-port data cache is provided having one port dedicated to servicing a local processor and a second port dedicated to servicing a system. The dual-port data cache is also capable of a high speed transfer of a line or lines of entries by placing the dual-port data cache in "burst mode." Burst mode may be utilized with either a read or a write operation. An initial address is latched internally, and a word line in the memory array is activated during the entire data transfer. A control circuit is utilized to cycle through and access a number of column addresses without having to provide a separate address for each operation.

REFERENCES:
patent: 4493033 (1985-01-01), Ziegler et al.
patent: 4633441 (1986-12-01), Ishimoto
patent: 4816997 (1989-03-01), Scales, III et al.
patent: 4825411 (1989-04-01), Hamano
patent: 5257236 (1993-10-01), Sharp
patent: 5261064 (1993-11-01), Wyland
patent: 5319768 (1974-06-01), Rastegar

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