Salicide compatible CMOS process with a differential oxide impla

Details Salicide compatible CMOS process with a differential oxide impla Salicide compatible CMOS process with a differential oxide impla

1992-11-17

1995-03-21

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 44, 437 57, 437200, 437192, H01L 21336

Patent

active

053995139

ABSTRACT:
The present process comprises the use of a differential oxidation of the source/drain regions to permit elimination of the p+ implant mask normally required for formation of p-channel device in a CMOS process. A DDD procedure provides protection against hot-electron effects. A second oxide spacer is included to allow formation of salicide at the contacts to provide low sheet resistance.

REFERENCES:
patent: 4314857 (1982-02-01), Aitken
patent: 4356623 (1982-11-01), Hunter
patent: 4358890 (1982-11-01), Heller et al.
patent: 4470852 (1984-09-01), Ellsworth
patent: 4474624 (1984-10-01), Matthews
patent: 4480375 (1984-11-01), Cottrell et al.
patent: 4753898 (1988-06-01), Parrillo et al.
patent: 4771014 (1988-09-01), Liou et al.
patent: 4775642 (1988-10-01), Chang et al.
patent: 4949136 (1990-08-01), Jain
patent: 4963504 (1990-10-01), Huang
patent: 5091763 (1992-02-01), Sanchez
patent: 5219784 (1993-06-01), Solheim
Lai, Fang-shi J., et al., "A Highly Latchup-Immune 1-.mu.m CMOS Technology Fabricated with 1-Me V Ion Implantation and Self-Aligned TiSi.sub.2," IEEE Transactions on Electron Devices, vol. ED-33, No. 9, Sep. 1986, pp. 1308-1320 (New York).
Chen, M-L., et al., "A High Performance Submicron CMOS Process with Self-Aligned Chan-Stop and Punch-Through Implants (Twin-Tub V)," International Electron Devices Meeting Technical Digest, Dec. 7-10, 1986, pp. 256-259 (Los Angeles).
L. C. Parrillo et al., Twin-Tub CMOS II --An Advanced VLSI Technology, IEDM '82, pp. 706-709.
Fair et al., Modeling Physical Limitations on Junction Scaling of CMOS, IEEE Trans. on Electron Devices, ED-31, No. 9, Sep. 1984, pp. 1180-1185.
Scott, et al., Considerations for Scaled CMOS Source/Drains, Reprint -IEDM '81, pp. 538-541.
R. R. Doering et al., A High Performance 1 .mu.m CMOS Process for VLSI Applications, IEEE 1985 Custom Integrated Circuits Conference, pp. 196-198.
A. C. Hui et al, An Oxide Masked P+ Source/Drain Implant for VLSI CMOS, IEDM '82, pp. 698-701.
Wolf et al., Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, 1986, pp. 397-399.
H. Mikoshiba et al., Comparison of Drain Structures in n-Channel MOSFETS, IEEE Trans. on Electron Dev., ED-33, No. 1, Jan. 1986, pp. 140-144.
J. Agraz-Guerena et al., Twin-Tub III -A Third Generation CMOS Technology, IEDM '84, pp. 63-66.
L. C. Parrillo et al., Twin-Tub CMOS --A Technology for VLSI Circuits, IEDM '80, pp. 752-755.

Affiliated with

Also associated with

Rating

Salicide compatible CMOS process with a differential oxide impla does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Salicide compatible CMOS process with a differential oxide impla, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Salicide compatible CMOS process with a differential oxide impla will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1148701