Self-testing and self-configuration in an integrated circuit

Details Self-testing and self-configuration in an integrated circuit Self-testing and self-configuration in an integrated circuit

1991-06-03

1993-11-09

Canney, Vincent P.

Excavating

371 224, 371 225, G11C 2900

Patent

active

052609464

ABSTRACT:
Integration at the chip level is supported by an architecture for self-testing and self-configuration of an integrated circuit. Self-testing requires the generation of test signals based on primary root polynomials, application of the test signals to functionally redundant modules, and evaluation of the response of the modules to the test signals. The response produced by a module is compared against the response predicted from error-free operation of the module. Modules whose responses correspond to the expected responses are interconnected for circuit operation. All of the architecture for self-testing and self-configuration is integrated with the tested and configured modules.

REFERENCES:
patent: 4959832 (1990-09-01), Bardell, Jr.
patent: 5138619 (1992-11-01), Fasang et al.
patent: 5195097 (1993-03-01), Bogholtz, Jr. et al.

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