1994-10-13
1996-12-31
Beausoliel, Jr., Robert W.
Excavating
371 251, 371 204, 3241581, G01R 3128
Patent
active
055901379
ABSTRACT:
A semiconductor IC tester is capable of undertaking a double-speed test for a IC device under test wherein the test pattern application and resulted signal comparison are performed both in the first half and the latter half of a test cycle of the IC tester without sacrificing the number of test pins. In the double-speed mode, the generating speed of test patterns is doubled as follows. In the first half of the test cycle, a flip-flop is set or reset at the timings of the outputs of first and second delay circuits, respectively. Moreover, in the latter half of test cycle, the flip-flop is set or reset at the timings of the output of third and fourth delay circuits, respectively, which are used usually as enabling and disabling a driver which generates a final form of test signal to the device under test. Threshold voltage values for first and second comparators are set to the same value, the compared result in the first half of test cycle is taken from the first comparator, and the compared result in the latter half is taken from the second comparator. The double-speed test may be applied to IC devices having input-only pins and output-only pins.
REFERENCES:
patent: 4497056 (1985-01-01), Sugamori
patent: 4928278 (1990-05-01), Otsuji et al.
patent: 5172047 (1992-12-01), Funakura
patent: 5430737 (1995-07-01), Yamashita et al.
Advantest Corporation
Beausoliel, Jr. Robert W.
Iqbal Nadeem
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