Phase-locked loop and resulting frequency multiplier

Details Phase-locked loop and resulting frequency multiplier Phase-locked loop and resulting frequency multiplier

1991-09-18

1993-11-09

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307271, 307603, 307606, 328155, 328 55, 328 15, H03K 500, H03L 700

Patent

active

052606082

DESCRIPTION:

BRIEF SUMMARY
CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to the following copending applications of applicant: Ser. No. 07/727,430 filed Jul. 9, 1991, corresponding to French 90.08811 filed Jul. 11, 1990. Resultant System for Digital Transmission of Serial Data", U.S. Ser. No. 07/727,429 filed Jul. 9, 1991, corresponding to French 90.08812 filed Jul. 11, 1990. System", U.S. Ser. No. 07/727,843, filed Jul. 9, 1991, corresponding to French 90.08813 filed Jul. 11, 1990.
The subject matter of the aforenoted U.S. applications is hereby incorporated herein by reference.


DESCRIPTION



Technical Field of the Invention

The invention relates to a phase-locked loop and to a resulting frequency multiplier.


BACKGROUND

The conventional phase-locked loop is currently known by the acronym PLL. A PLL includes the following: a phase comparator for, receiving an input signal and a negative feedback signal; a filter connected to receive the output signal of the phase comparator; and a voltage controlled oscillator (VCO), which receives the output signal of the filter, furnishes the output signals of the PLL, and commands a negative feedback loop to produce the negative feedback signal to be applied to the phase comparator. The filter has a relatively low cutoff frequency relative to the frequency of the oscillator. The oscillator is generally one that generates free oscillations at a frequency controlled analogously for variation within a predetermined band of frequencies. With this PLL, a multiplier that multiplies the frequency by N is formed by inserting a divisor that divides the frequency by N into the negative feedback loop.
The use of a PLL has several major disadvantages. The first disadvantage is the relatively long time to obtain stable phase locking at the desired operating frequency of the PLL. This disadvantage arises at the moment the PLL is started up, or upon a change of the desired operating frequency of the PLL. The length of time to establish a stable PLL function is due to the presence of the negative feedback loop and depends on the electrical characteristics of the PLL. The most important characteristic is the value of the cutoff frequency of the filter with respect to the desired operating frequency of the PLL. The lower the cutoff frequency, the longer the establishment time. However, the lower the cutoff frequency of the filter, the better the phase-locking effectiveness. Consequently, a relatively major delay for establishment of correct operation of a PLL has to be allowed. Ordinarily this delay is on the order of several milliseconds and accordingly corresponds to the passage of numerous data that the PLL cannot process.
A second disadvantage of the use of a PLL is its sensitivity to induced electrical noise in the analog command signal of the VCO, which results in temporary instability (jitter) in the output frequency of the PLL.
A third disadvantage is that the operating frequency band of a PLL is relatively narrow, for two reasons. First, the two input signals of the phase comparator do not have the same phase or the same frequency. Making a comparator with a wide frequency bandwidth and a wide phase range band proves to be quite difficult and very bulky in an integrated circuit. Secondly, it has been seen that the analog command of the oscillator is very sensitive to electrical noise. Consequently, the noise occurring within a wide frequency band would cause very much major variations in frequency in the output signal and would compromise the operating stability of the PLL.
The analog phase command of the oscillator of a PLL also causes a fourth disadvantage. This disadvantage is thrown into an especially high relief in the following example. Currently, activating a transmission link in an integrated circuit causes relatively high heat dissipation, on the order of 0.5 W, for example. Consequently, if a large number of links (32, for example) is to be integrated, it is possible only to activate a small number (4 or 8). One method consists of making the other links dormant, and

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IBM Technical Disclosure Bulletin, vol. 26, No. 3A, Aug. 1983, pp. 990, 991, Hernandez, Jr. "Frequency Multiplier Using Delay Circuits".

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