Multi-port memory with serially connected output elements

Details Multi-port memory with serially connected output elements Multi-port memory with serially connected output elements

1992-04-27

1995-05-02

Elmore, Reba I.

Boots, shoes, and leggings

364DIG1, 3642448, 3649659, G06F 1300

Patent

active

054127890

ABSTRACT:
Address bits AU1 to AU4 designating rows of a memory 1 at random are successively given thereto. Respective Q lines of each row of the memory 1 are connected in series to register groups SR-R1 to SR-R4. An address bit of a row designated with AU1 to AU4 is stored in each register group. Respective data of the register groups SR-R1 to SR-R4 is supplied to output ports SO1 to SO4 in series by selectors SL1 to SL4. Instead of the register groups SR-R1 to SR-R4 and the selectors SL1 to SL14, shift registers can be used.

REFERENCES:
patent: 4541075 (1985-09-01), Dill et al.
patent: 4633441 (1986-12-01), Ishimoto
patent: 4821226 (1989-04-01), Christopher et al.
patent: 4987559 (1991-01-01), Miyauchi et al.
patent: 5065369 (1991-11-01), Toda
patent: 5170157 (1992-12-01), Ishii
patent: 5206831 (1993-04-01), Wakamatsu

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