Excavating
Patent
1993-10-01
1995-11-21
Canney, Vincent P.
Excavating
371 212, G01R 3128
Patent
active
054694434
ABSTRACT:
A memory is tested by subjecting the memory to three phases of testing. In the first phase, a first address in the memory is initialized by writing an initial set of data to the address. Then data is read from the address just written to and this data is modified to produce a set of modified data. The modified data is then written to another address in the memory. The steps of reading, modifying, and writing modified data back to the memory are repeated until all addresses in the memory have been written to. Thereafter, the data values stored in the memory are compared to a reference list of data values to determine whether the memory contains a defect. In phase two, the steps of phase one are repeated except that the first address in the memory is initialized by writing a set of data which is the complement of the initial set of data used in phase one. Phase two, in effect, complements the contents of each address in the memory to ensure that each cell in the memory is written with both a 0 and a 1. At the end of phase two, the data values stored in the memory are again compared to a list of reference data values to determine whether the memory contains a fault. In phase three, an address in the memory is first selected. Data is then read from the selected address and modified to produce a set of modified data. The modified data is written back to the selected address. The steps of reading, modifying, and writing modified data back to the selected address are repeated a selected number of times. Thereafter, another address in the memory is selected and the process described above is repeated. After all of the addresses in the memory have been selected, the data values stored in the memory are once again compared to a reference list of data values. Using the three-phase test described above, all stuck-at, address uniqueness, address coupling, and bit coupling (within a storage location) faults in the memory are provoked and detected.
REFERENCES:
patent: 4891811 (1990-01-01), Ash et al.
patent: 5258986 (1993-11-01), Zerbe
patent: 5315553 (1994-05-01), Morris
patent: 5357523 (1994-10-01), Bogholtz, Jr. et al.
Canney Vincent P.
HaL Computer Systems, Inc.
Truong Phong K.
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