Data protection and error correction, particularly for general r

Details Data protection and error correction, particularly for general r Data protection and error correction, particularly for general r

1993-03-25

1995-05-02

Nguyen, Hoa T.

Excavating

371 491, 371 492, 371 493, G06F 1110

Patent

active

054126711

ABSTRACT:
A data protection and correction scheme is implemented by providing main and shadow stores for groups of data bits from a segmented data word. The data bits are divided into even and odd address groups for storage into even and odd storage sections. Each group of 3 bits from a 36-bit data word is supplied in uncomplemented form to even and odd address main stores and in a complemented form to even and odd address shadow stores. By storing the complemented parity bit with the uncomplemented data and the uncomplemented parity bit with the complemented data, the odd parity of the input data is converted to an even parity which may be checked upon read-out from the main store. If this parity test fails, the shadow store is accessed to supply the correct data. When a write address and a read address attempt to access the same storage address a conflict is detected and input data and parity are directly supplied to an output multiplexor. In the preferred embodiment the data is supplied to the general register set of the receiving processor.

REFERENCES:
patent: 3340506 (1967-09-01), Mayer
patent: 4224681 (1980-09-01), Lewine
patent: 4271519 (1981-06-01), Hall
patent: 4679195 (1987-07-01), Dewey
patent: 5008886 (1991-04-01), Chinnaswamy et al.
patent: 5140597 (1992-08-01), Araki

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