Non-volatile semiconductor memory device capable of storing mult

Static information storage and retrieval – Floating gate – Particular biasing

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365184, 36518901, 365168, G11C 1156

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active

054126010

ABSTRACT:
An electrically erasable non-volatile semiconductor memory device comprising a plurality of row lines and column lines, a plurality of memory cells connected in a matrix to the plurality of row lines and column lines, a selection circuit for selecting a desired one of the plurality of memory cells, and write-control circuit for writing data into the plurality of memory cells. The write-control circuit is adapted to preset at least four voltage signals having different voltage values, and to select one of four voltage signals according to a data signal externally applied thereto and applying the selected voltage signal to the selected memory cell. Also included is read-control circuit for reading out data written into the selected memory cell and converting the data read-out from the selected memory cell into a data signal corresponding to one of the four voltage signals.

REFERENCES:
patent: 4809224 (1989-02-01), Suzuki et al.
patent: 5012448 (1991-04-01), Matsuoka et al.
patent: 5043940 (1991-08-01), Harari
patent: 5119330 (1992-06-01), Tanagawa
A 16 kb Electrically Eraseable Volatile Memory 1980 IEEE ISSCC Dig. Tech. Pap., pp. 152-153, 271, 1980.
Analysis and Modeling of Floating-Gate EPROM Cells IEEE Trans. Electron Devices 1986, Jun., ED-33, No. 6, pp. 835-844.
Semiconductor MOS Memory and Method of Using the Same, Nikken Kogyo Newspaper Co. 1990, pp. 96-101.

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