Floating point computing device for simplifying procedures accom

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3647365, G06F 738, G06F 700

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054693772

ABSTRACT:
A floating point computing device having a mantissa register for storing a mantissa of a floating-point number, a detecting circuit for determining the bit states of the consecutive bits of the mantissa register, and a round and normalize data generating circuit for generating, on the basis of the output of the detecting circuit, information for controlling rounding and normalization. The detecting circuit determines whether all the bits of the digits of the mantissa register are 0 or whether they are 1. In response to the output of the detecting circuit, the round and normalize data generating circuit generates information including the kind of rounding operation and a rounding constant. When the resultant mantissa is negative, the kind of computation is indicative of subtraction. Consequently, the complement processing of the mantissa and the rounding operation are executed at the same time.

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Computer Architecture and Organization, John P. Hayes, pp. 197-198 (undated).

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