Process for forming integrated capacitors

Fishing – trapping – and vermin destroying

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437 47, 437 52, 437919, 148DIG14, H01L 2170

Patent

active

055894160

ABSTRACT:
Disclosed is a technique for forming integrated capacitors using a sequence of process steps that is fully compatible with standard silicon gate MOS integrated circuit processing. The capacitor comprises a polysilicon-oxide-TiN/metal combination. The lower plate, i.e. polysilicon plate, is interconnected at the gate level and the upper plate is interconnected typically at metal one.

REFERENCES:
patent: 5130267 (1992-07-01), Kaya et al.
patent: 5173437 (1992-12-01), Chi
patent: 5227325 (1993-07-01), Gonzalez
patent: 5356826 (1994-10-01), Natsume
patent: 5470775 (1995-11-01), Nariani

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