Read-only memory

Details Read-only memory Read-only memory

1991-10-22

1994-01-18

LaRoche, Eugene R.

Static information storage and retrieval

Interconnection arrangements

365 94, 365103, G11C 1140

Patent

active

052804429

ABSTRACT:
A read-only memory includes columns of memory cell arrays, a plurality of banks formed by dividing each column of the memory cell arrays along the columns, sub-bit lines disposed between adjacent banks situated along the rows and connected to a transistor of each memory cell, and main-bit lines disposed between every two other columns of the memory cell arrays and extending along the columns, wherein the sub-bit lines are divided into sets of three sub-bit lines connected to a pair of adjacent banks situated along the rows, and one end of each center sub-bit line being connected to a first main-bit line through a first selector transistor, the first main-bit line passing through one side of the set to which the center bit-line belongs, and the other end of the sub-bit line being connected to a second main-bit line through a second selector transistor, the second main-bit line passing through the other side of the set to which the center sub-bit line belongs, the two outer sub-bit lines being directly connected to the main-bit lines adjacent to the set of banks, respectively.

REFERENCES:
patent: 4970685 (1990-11-01), Koyanagi
patent: 5111428 (1992-05-01), Liang et al.
Nakahara et al., International Conference on Wafer Scale Integration, (Jan. 23-25, 1990) 1990:57-59.
Yamada et al., IEEE Journal of Solid-State Circuits (Feb. 1988) 23(1):20-26.

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