Memory circuit including an EEPROM provided with unique addressi

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377 50, G06F 1520

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active

052804380

ABSTRACT:
A counter is provided which updates a most-recent counter value to be stored in a non-volatile memory. The counter includes a counter circuit for receiving a series of count pulses defining a count operation and outputting a series of coded binary signals in response thereto. Each one of the series of coded binary signals includes at least first digit data and second digit data. A selecting circuit is coupled to the non-volatile memory and the counter circuit for logically selecting, in response to each respective second digit data, a first select memory cell in the non-volatile memory for which the corresponding first digit data is to be stored. A write control circuit is coupled to the non-volatile memory and the counter circuit for writing a subsequent first digit data over the first select memory cell when a counting operation of the respective digit value has not reached completion, and writing the subsequent first digit data in a different memory cell when a counting operation of the respective digit value has reached completion.

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