Transistor circuit for holding peak/bottom level of signal

Details Transistor circuit for holding peak/bottom level of signal Transistor circuit for holding peak/bottom level of signal

1993-08-04

1995-11-21

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 94, 327 62, G01R 1900, H03K 5153

Patent

active

054690900

ABSTRACT:
A transistor circuit for detecting and holding a peak or bottom level of an input voltage includes a first transistor connected between a first power line and an output terminal, a capacitor connected between the output terminal and a second power line, a second transistor supplied with the input voltage and producing a current responsive to the input voltage, and a current mirror circuit supplied with the current from the second transistor as an input current and discharging the capacitor with an output current. The output current of the current mirror circuit is preferably designed to be smaller than a charging current to the capacitor from the first transistor.

REFERENCES:
patent: 3694748 (1972-09-01), Hekimian
patent: 4987323 (1991-01-01), Fujita
patent: 5038055 (1991-08-01), Kinoshita
patent: 5120995 (1992-06-01), Abdi
patent: 5254881 (1993-10-01), Leonowich
patent: 5315168 (1994-05-01), Norton, Jr.

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