Virtual address translator

Details Virtual address translator Virtual address translator

1976-09-24

1978-06-20

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 920, G06F 1300

Patent

active

040965686

ABSTRACT:
A virtual address translator comprises a content addressed memory and a word addressed memory. A task name and subsegment number from a virtual address supplied by a processor are employed as a key word to search a content addressed memory and read out a subsegment descriptor if the key word is matched. The subsegment descriptor includes an absolute base address which is added to a deflection field to obtain an absolute memory address. The memory address is applied to a memory to permit transfer of a word between the processor and the memory. The processor may present any one of several task names depending upon whether the memory reference is made for an instruction or data for the processor, or for an instruction or data for an I/O connected to the processor. Bounds, residency and access privileges are checked using the subsegment descriptor. If a search of the content addressed memory reveals that the desired subsegment descriptor is not in the word addressed memory, the translator obtains the descriptor from memory and then generates the desired absolute memory address. The translator is provided with circuits generating values which indicate the efficiency of its operation. Controls are provided for selecting any one of several widths for the subsegment and deflection fields of virtual addresses received from the processor.

REFERENCES:
patent: 3412382 (1968-11-01), Couleur et al.
patent: 3768080 (1973-10-01), Boger et al.
patent: 3800286 (1974-03-01), Brown et al.
patent: 3938100 (1976-02-01), Steiner
patent: 3976977 (1976-08-01), Porter et al.
patent: 3979726 (1976-09-01), Lange et al.

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