Method for improving characteristics of parasitic PN diodes in s

Details Method for improving characteristics of parasitic PN diodes in s Method for improving characteristics of parasitic PN diodes in s

1993-08-30

1995-05-02

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 47, 437 60, H01L 2170, H01L 2700

Patent

active

054119103

ABSTRACT:
The present invention relates to a method for improving characteristics of parasitic pn diodes in a static random access memory using a PMOS TFT.
Disclosed herein is a method for improving characteristics of parasitic pn diodes which comprises the step of implanting impurities having a type opposite to that of impurities doped in a previously formed polysilicon layer in a contact area of the previously formed polysilicon layer.

REFERENCES:
patent: 4890144 (1989-12-01), Teng et al.
patent: 5170227 (1992-12-01), Kaneko et al.

Affiliated with

Also associated with

Rating

Method for improving characteristics of parasitic PN diodes in s does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for improving characteristics of parasitic PN diodes in s, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for improving characteristics of parasitic PN diodes in s will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1136710