Flash EEPROM array with P-tank insulated from substrate by deep

Details Flash EEPROM array with P-tank insulated from substrate by deep Flash EEPROM array with P-tank insulated from substrate by deep

1992-05-28

1995-05-02

Thomas, Tom

Fishing, trapping, and vermin destroying

437 48, 437 43, H01L 2170

Patent

active

054119081

ABSTRACT:
In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated memory circuit. The deep N-tank allows application of a negative voltage of perhaps -8 V to the P-tank encasing the memory array. Application of that negative voltage permits the cells of the memory array to be programmed with voltage pulses having a peak value of about +10 V, rather than the +18 V peak value of prior-art memory arrays. Because the external circuitry, such as the wordline driver circuit, need drive the wordlines at +10 V rather than +18 V, the invention permits construction of that external circuitry using thinner gate insulators and space-saving shorter dimensions.

REFERENCES:
patent: 4451905 (1984-05-01), Moyer
patent: 4784966 (1988-11-01), Chen
patent: 5225700 (1993-07-01), Smayling
patent: 5238860 (1993-08-01), Sawada et al.
patent: 5243559 (1993-09-01), Murai

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