Semiconductor memory device having function of checking and corr

Details Semiconductor memory device having function of checking and corr Semiconductor memory device having function of checking and corr

1988-05-18

1990-06-26

Smith, Jerry

Excavating

G06F 1110

Patent

active

049378309

ABSTRACT:
A semiconductor memory device includes a memory cell array; a sense amplifying circuit, operatively connected to the memory cell array, for sensing the information bits and the check bits; a latch circuit, operatively connected to the sense amplifying circuit, for latching the information bits and the check bits sensed by the sense amplifying circuit; and a circuit for correcting an error in logical level in the information bits.
The latch circuit latches the logical level of the bit signal at a predetermined time after a change in an address signal. Thus, regardless of whether or not a time at which the logical level of the bit signal of the sense amplifying circuit is settled coincides, the influence is not exerted on the operation of the subsequent error correcting circuit. As a result, it is possible to prevent the appearance of a hazard in the output data and, accordingly, to realize a perfect ECC relief, while increasing a reliability in the reading operation as a device.

REFERENCES:
patent: 4653052 (1987-03-01), Doi
patent: 4703453 (1987-10-01), Shinoda
patent: 4726021 (1988-02-01), Horiguchi
patent: 4780875 (1988-10-01), Sakai
"Error Check and Correction for Soft Error of Dynamic Random-Access Memory", IBM TDB, V31, No. 10, 3/1989, pp. 58-60.
"THAM 10.4: A 64Kb CMOS EEROM with On-chip ECC", 1984 IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 23, 1984.

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