Static random access memory device with power down function

Details Static random access memory device with power down function Static random access memory device with power down function

1989-03-22

1990-06-26

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

365195, G11C 1134

Patent

active

049377922

ABSTRACT:
A static random access memory device is comprised of a write mode detector for detecting a signal state transition of a write enable signal changing to an active state, an input data transition detector for detecting a transition of the input data supplied from exterior, during a contamination of the active state of the write enable signal, a power down timer for generating a pulse signal with a predetermined pulse width in response to either of the detecting signals outputted from the write mode detector and input data transition detector, a gate circuit for permitting the output data from a row decoder to be transferred to memory cells during a period that the power down timer generates a pulse signal, and for inhibiting that data transfer during a period that the power down timer rests, and a write circuit control circuit allowing a write circuit to supply write data to the bit line pair during a period that the power down timer generates a pulse signal, and prohibiting that write data transfer during a period that the power timer rests.

REFERENCES:
patent: 4669064 (1987-05-01), Ishimoto
patent: 4689771 (1987-08-01), Wang et al.
patent: 4707809 (1987-11-01), Ando
Gubbels et al., "A 40-ns/100-pF Low-Power Full-CMOS 256K (32K X 8) SRAM", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 741-747.

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