Patent
1988-03-16
1990-06-26
James, Andrew J.
357 236, 357 239, 357 233, H01L 2702
Patent
active
049376454
ABSTRACT:
A semiconductor device comprising n-channel MISFETs and p-channel MISFETs each having a gate electrode having side walls selectively provided with side wall insulating films, and a method of manufacturing such a semiconductor device. The side wall insulating films covering the side walls of the gate electrodes of the MISFETs are formed by etching a single insulating film, formed simultaneously over all the MISFETs in a single processing step. The length of the side wall insulating films of the gate electrode of the n-channel MISFET, along the direction of channel length, is about 0.3 .mu.m or above. The length of the side wall insulating films of the gate electrode of the p-channel MISFET, along the direction of channel length, is smaller than the length of the side wall insulating films of the n-channel MISFET.
REFERENCES:
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4616401 (1986-10-01), Takeuchi
patent: 4742018 (1988-05-01), Kimura et al.
patent: 4811076 (1989-03-01), Tigelaar et al.
IEDM Technical Digest, Dec. 1985, pp. 56-63.
Ootsuka Fumio
Tsuchiya Osamu
Hitachi , Ltd.
James Andrew J.
Prenty Mark
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