Design verification system using expect buffers

Details Design verification system using expect buffers Design verification system using expect buffers

1997-03-27

1999-08-10

Teska, Kevin J.

39550034, G06F 9455

Patent

active

059371820

ABSTRACT:
A design verification system for simulating designs and evaluating the simulation results against a set of expected events. A set of expected events are generated and loaded into an expect buffer. As the simulation proceeds, each modelled device collects data on each event into an event record. Each event record is compared against the set of expected events. If the set of expected events contains an entry that matches the event record, the matching entry is removed from the expect buffer. If a matching entry is not found then the event record is flagged as an error. The system is flexible to design changes and efficient as the exact ordering of events is not critical to the simulation outcome.

REFERENCES:
patent: 4807182 (1989-02-01), Queen
patent: 5101424 (1992-03-01), Clayton et al.
patent: 5327361 (1994-07-01), Long et al.
patent: 5488648 (1996-01-01), Womble
patent: 5794005 (1998-08-01), Steinman
Wagner & Keane, "A Strategy to Verify Chassis Controller Software-Dynamics, Hardware, and Automation," IEEE Transactions on Systems, Man, and Cybernetics-Part A: Systems and Humans, vol. 27 No. 4, pp. 480-493, Jul. 1997.

Affiliated with

Also associated with

Rating

Design verification system using expect buffers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Design verification system using expect buffers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Design verification system using expect buffers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1128833