Semiconductor memory device having burn-in test function

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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365201, 365226, G11C 700

Patent

active

059369108

ABSTRACT:
In a semiconductor memory device including a plurality of word lines connected to memory cells, a word line level generating circuit for generating a suitable word line level generating voltage higher than a power supply voltage and a plurality of word line drivers, each for driving one of the word lines using the word line level generating voltage a plurality of row decoders activate a first number of the word line drivers in a usual mode and activate a second number of the word line drivers in a burn-in test mode. The second number is larger than the first number. A control circuit detects the word line level generating voltage and uses feedback to control the voltage to a definite level.

REFERENCES:
patent: 4751683 (1988-06-01), Wada et al.
patent: 5590079 (1996-12-01), Lee et al.
patent: 5608674 (1997-03-01), Yabe et al.

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