Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

1998-07-23

1999-08-10

Le, Vu A.

Static information storage and retrieval

Floating gate

Particular biasing

36518527, 36518518, 36518909, G11C 700

Patent

active

059368918

ABSTRACT:
It is an object of the invention to provided an electrically erasable and programmable non-volatile semiconductor memory device, in which misread of a datum stored in a memory cell can be avoided by suppressing floating of the potentials of a memory cell source wire and a word wire in case that the operation of the memory device shifts from erasing pulse application to erase verify. Two transistors with different current-driving capabilities are connected in parallel and inserted between the memory cell source wire and the ground plane. When the operation of the memory device shifts from erasing pulse application to erase verify, a N-type transistor with lower current-driving capability turns on at fist, thereby the potential of the memory cell source wire is slowly reduced, and the other transistor with higher current-driving capability turns on afterward. After the memory cell source wire is connected with the ground plane and its potential is perfectly stabilized, the datum stored in the memory cell can be normally read.

REFERENCES:
patent: 4425632 (1984-01-01), Iwahshi et al.
patent: 5483485 (1996-01-01), Maruyama
patent: 5521864 (1996-05-01), Kobayashi et al.

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