Input frequency converter to increase input frequency range of a

Details Input frequency converter to increase input frequency range of a Input frequency converter to increase input frequency range of a

1993-10-20

1994-09-13

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

328155, 328 15, H03K 2100

Patent

active

053475585

ABSTRACT:
A front end scalar to a frequency multiplier such as a synchronous delay line (SDL) allows the SDL to operate at a single clock frequency for all multiplier coefficients and input frequencies and provides for maximum SDL design margins. A frequency multiplier of this type relies upon a feedback voltage to maintain a desired output clock frequency. So long as the input clock frequency is within predetermined limits, the feedback voltage will maintain the output frequency at a desired frequency for which the SDL has been optimized. As the input frequency approaches the upper or lower limit for which an SDL basic building block has been optimized, it may become impossible for an SDL to provide frequency lock since control voltage is already below or above V.sub.cc /2 due to a lower or a higher input frequency. The invention operates to ensure that the input frequency to the SDL is always close to the frequency for which the SDL has been optimized by changing the input frequency to a frequency which is at or near the frequency for which a SDL has been optimized and thereby eliminate the input frequency dependency of the SDL.

REFERENCES:
patent: 4443887 (1984-04-01), Shiramizu
patent: 4545063 (1985-10-01), Kaminaru
patent: 4980585 (1990-12-01), Bazes
patent: 4991187 (1991-02-01), Herold et al.

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