Processor architecture supporting speculative, out of order exec

Details Processor architecture supporting speculative, out of order exec Processor architecture supporting speculative, out of order exec

1996-11-14

1998-08-18

Donaghue, Larry D.

395388, 395392, 395391, 395393, 395381, 395586, 395581, G06F 930, G06F 938, G06F 1582

Patent

active

057970254

ABSTRACT:
A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.

REFERENCES:
Pleszkun et al. "The Performance Potential of Multiple Functional Unit Processors" 1988 IEEE.
Pleszkun et al. "WISQ: A Restartable Architecture Using Queues" 1987 ACM.
Sohi; "Instruction Issue Logic for High Performance Interruptible, Multiple Functional Unit, Pipelined Computer", U of Wisconsin, G.S. Tech Report 1987.

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