Multiplication element including a wallace tree circuit having a

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36476003, G06F 752

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active

058674152

ABSTRACT:
A multiplication element including a plurality of partial product generating circuits for inputting a multiplicand and a plurality of modified multipliers obtained based on a multiplier, and for generating 0.sup.th partial products corresponding to the modified multipliers, a Wallace tree circuit formed by an array of rows comprising at least one i-th first (1.ltoreq.i) adder, and a final adder for adding the pair of final partial products so as to obtain a result of the multiplication of the multiplicand by the multiplier. Each of the at least one i-th adder comprises a plurality of bits arranged in columns. The Wallace tree circuit is adapted to add a predetermined number of j-th (0.ltoreq.j.ltoreq.i-1) partial products so as to generate i-th partial products, add partial products like a tree while sequentially decreasing the number of the partial products, and output a pair of final partial products. The at least one i-th first adder of the Wallace tree circuit is separated on a particular bit of the multiplication result as a boundary into high and low order adders and the high and lower order adders are provided in rows which are different from each other.

REFERENCES:
patent: 5257217 (1993-10-01), Chiu
patent: 5325320 (1994-06-01), Chiu
patent: 5426599 (1995-06-01), Machida
patent: 5465226 (1995-11-01), Goto
patent: 5504915 (1996-04-01), Rarick
patent: 5544084 (1996-08-01), Fukumoto

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