Latchup-preventing CMOS device

Details Latchup-preventing CMOS device Latchup-preventing CMOS device

1986-04-21

1987-02-24

Edlow, Martin H.

357 55, 357 59, 357 60, 357 238, H01L 2702, H01L 2906

Patent

active

046461230

ABSTRACT:
A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 .mu.m, as well as a method for fabricating the device, is disclosed.
The inventive CMOS device includes a latchup-preventing, polysilicon-filled trench formed in the semiconductor substrate between the n- and p-channel FETs of the device. The polysilicon-filled trench is essentially free of crack-inducing voids, and achieves a width less than 10 .mu.m, because the angle between the trench sidewall and a perpendicular drawn to the substrate surface is greater than, or equal to, about 5 degrees but less than about 10 degrees. Also, a thickness of the polysilicon deposited into the trench is greater than half the width of the trench.

REFERENCES:
patent: 4231057 (1980-10-01), Momma et al.
patent: 4477310 (1984-10-01), Dark et al.
T. Fukushima et al., "A High Speed Schottky 4k-Bit PROM Using Diffused Eutectic Aluminum Process (Deap)," Proceedings of the 11th Conference (1979 International) on Solid State Devices, Tokyo, 1979; Japanese Journal of Applied Physics, vol. 19 (1980) Supplement 19-1, pp. 175-180.
S. Y. Chiang et al, "Trench Isolation Technology for MOS Applications," Journal of the Electrochemical Society, Aug. 1982, vol. 129, No. 8, p. 327C, Abstract 174 (abstract for the Fall Meeting of the Electrochemical Society held Oct. 17-21, 1982, in Detroit, Michigan).
S. Y. Chiang et al, "Trench Isolation Technology for MOS Applications," The Electrochemical Society Extended Abstracts, vol. 82-2, Abstract No. 174 (extended abstract for the Fall Meeting of the Electrochemical Society held Oct. 17-21, 1982, in Detroit, Michigan).
S. Y. Chiang et al, "Trench Isolation Technology for MOS Applications," Proceedings of the First International Symposium on VLSI Science and Technology, vol. 82-7, pp. 339-346 (proceedings of the Fall Meeting of the Electrochemical Society held Oct. 17-21, 1982, in Detroit, Michigan).
R. D. Rung et al, "Deep Trench Isolated CMOS Devices," IEDM Technical Digest, Dec. 1982, pp. 237-240.

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