Dynamic memory, a power up detection circuit, and a level detect

Details Dynamic memory, a power up detection circuit, and a level detect Dynamic memory, a power up detection circuit, and a level detect

1992-07-02

1994-09-13

Wambach, Margaret Rose

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072723, 307279, 307592, 307594, H03K 301, H03K 326

Patent

active

053471733

ABSTRACT:
A voltage level detection circuit is disclosed. The circuit is incorporated into a dynamic memory, integrated onto a single semiconductor substrate to which external voltage and reference potentials are applied. The dynamic memory contains an array of memory cells and circuitry for writing and reading information into and from the cells of the array. It contains an oscillator for generating an oscillator signal when the external voltge is above the reference potential. The voltage level detection circuitry is controlled by the oscillator signal, for controlling a voltage obtained from the external voltage, to the reading and writing circuitry and to the array to prevent the voltage from being applied unless the voltage at least of a predetermined minimum value. It may contain a circuit for sampling the obtained voltage during selected oscillator cycles to determine whether the obtained voltage is above the predetermined value. Other elements may be added to further enhance performance of the circuit.

REFERENCES:
patent: 4692904 (1987-08-01), Sato et al.
patent: 4886983 (1989-12-01), Taka

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