Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1993-08-12
1994-09-13
James, Andrew J.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257779, 257780, H01L 2348, H01L 2944, H01L 2952
Patent
active
053471628
ABSTRACT:
An interposer (preformed planar structure) is disposed between a die and a substrate (which may be another die). Through holes in the interposer facilitate controlled formation of reflow solder joints between conductive bumps on the die and corresponding conductive bumps of the substrate. In one embodiment, conductive elements embedded in the preformed planar structures extend at least partially into the through holes, forming electrical connections with the corresponding solder joints. The conductive elements can be used to electrically connect one solder joint to another within the interposer, and/or may extend beyond an edge of the interposer to provide for electrical probing of or connection to the solder joints. In one embodiment, the conductive elements are extended outside of the preformed planar structure to form "pins" or leads of the flip-chip structure. In another embodiment, a foil is disposed across a through hole, so that otherwise electro-galvanically incompatible solder balls on the die and the substrate will not corrode each other.
REFERENCES:
patent: 3388301 (1968-06-01), James
patent: 3429040 (1969-02-01), Miller
patent: 3624462 (1971-11-01), Phy
patent: 3811186 (1974-05-01), Larnerd et al.
patent: 3835531 (1974-09-01), Luttmer
patent: 3871014 (1975-03-01), King et al.
patent: 4190855 (1980-02-01), Inoue
patent: 4355463 (1982-10-01), Burns
patent: 4425501 (1984-01-01), Stauffer
patent: 4478915 (1984-10-01), Poss et al.
patent: 4545610 (1985-10-01), Lakritz et al.
patent: 4553036 (1985-11-01), Kawamura et al.
patent: 4636631 (1987-01-01), Carpentier et al.
patent: 4664309 (1987-05-01), Allen et al.
patent: 4700276 (1987-10-01), Freyman et al.
patent: 4700473 (1987-10-01), Freyman et al.
patent: 4733096 (1988-03-01), Horiguchi
patent: 4783722 (1988-11-01), Osaki et al.
patent: 4811082 (1989-03-01), Jacobs et al.
patent: 4825284 (1989-04-01), Soga et al.
patent: 4827118 (1989-05-01), Shibata et al.
patent: 4830264 (1989-05-01), Bitaillou et al.
patent: 4926241 (1990-05-01), Carey
patent: 4970575 (1990-11-01), Soga et al.
patent: 4970577 (1990-11-01), Ogihara et al.
patent: 5006673 (1991-04-01), Freyman et al.
patent: 5039628 (1991-08-01), Carey
patent: 5059553 (1991-10-01), Berndimaier et al.
patent: 5077633 (1991-12-01), Freyman et al.
patent: 5111279 (1992-05-01), Pasch et al.
patent: 5149958 (1992-09-01), Hallenbeck et al.
patent: 5168346 (1992-12-01), Pasch et al.
patent: 5258648 (1993-11-01), Lin
"Wafer-Chip Assembly For Large-Scale Integration", by Kraynak et al., IEEE Transactions On Electron Devices, vol. ED 1-5, No. 9, Sep. 1968, pp. 600-603.
James Andrew J.
Linden Gerald E.
LSI Logic Corporation
Monin, Jr. Donald L.
LandOfFree
Preformed planar structures employing embedded conductors does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Preformed planar structures employing embedded conductors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Preformed planar structures employing embedded conductors will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1122465