Excavating
Patent
1985-08-15
1987-08-18
Fears, Terrell W.
Excavating
371 50, 365200, 365201, G06F 1100, H03M 1300, G11C 700, G11C 2900
Patent
active
046882197
ABSTRACT:
A semiconductor memory device which has an error correcting circuit and employs a virtual two-dimensional matrix for correcting read data is provided. The device includes a redundant memory cell to replace a defective memory cell. When the selected memory cell has a previously determined hard error, the selected memory cell is replaced by the redundant memory cell. When the selected memory cell has a soft error or a hard error occuring after the determination of the previously determined hard error, the read data is corrected by the error correcting circuit.
REFERENCES:
patent: 4433388 (1984-02-01), Oosterbaan
patent: 4463450 (1984-07-01), Haeusle
patent: 4538245 (1985-08-01), Smarandoin et al.
patent: 4577294 (1986-03-01), Brown et al.
patent: 4639917 (1987-01-01), Furuta
Junzo Yamada 1984 IEEE, ISSCC Digest of Technical Paper pp. 104-105.
Fears Terrell W.
Fujitsu Limited
Koval Melissa J.
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