Hierarchical configurable gate array

Details Hierarchical configurable gate array Hierarchical configurable gate array

1986-07-07

1987-08-18

Edlow, Martin H.

Boots, shoes, and leggings

357 40, 357 70, 357 68, 364491, H01L 2710, H01L 2702, H01L 2348, H01L 2952

Patent

active

046880720

ABSTRACT:
A hierarchical configurable gate array is disclosed and includes a plurality of cluster regions (10,20,30,40) arranged in different levels. The first level cluster (10) includes an integral number N multi-terminal components for providing canonical functions. The second level cluster (20) includes N first level clusters; and higher level clusters (30,40) each includes N clusters of the next lower level. Interconnect regions (13,15,17,19) are provided within each cluster for interconnections between the N elements of each level. Selected input or output ports for each element of a cluster are available for interconnection at more than one location.

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Patents Abstracts of Japan, vol. 7, No. 40 (E-159)(1185), Feb. 17, 1983, (Tokyo, JP) & JP, A, 57192061 (Hitachi Seisakusho K.K.).
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IBM Technical Disclosure Bulletin, vol. 20, No. 8, Jan. 1978, B. C. Fox et al., "Large-Scale Integration Modeling Technique", pp. 3129-3130.
IEEE Journal of Solid State Circuits, vol. SC-16, No. 5, Oct. 1981, F. Borgini et al., "CMOS/SOS Automated Universal Array", pp. 563-570.

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