Method for fabricating an interconnect structure in an integrate

Details Method for fabricating an interconnect structure in an integrate Method for fabricating an interconnect structure in an integrate

1993-07-06

1994-09-13

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437192, H01L 21283

Patent

active

053468600

ABSTRACT:
A method for fabricating an interconnect structure in an integrated circuit. A first conductive layer is formed over an underlying region in the integrated circuit. The underlying region may be, for example, a semiconductor substrate or a gate electrode. A buffer layer is then formed over the first conductive layer, followed by the formation of an insulating layer over the buffer layer. The insulating layer and the buffer layer are patterned to define a form for the interconnect structure. A second conductive layer is then formed over the integrated circuit, and portions of the first conductive layer, the second conductive layer, and the buffer layer are silicided to form the interconnect structure.

REFERENCES:
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patent: 4977098 (1990-12-01), Yu et al.
patent: 5121186 (1992-06-01), Wong et al.
patent: 5173450 (1992-12-01), Wei
Y. S. Huang, et al. "Ti-Silicide with improved thermal stability using silicidation through oxide on amorphous silicon substrates" J. Mat. Sci. Lett. 12 (1993) pp. 1726-1728.

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