Method for fabricating an insulated gate control thyristor

Details Method for fabricating an insulated gate control thyristor Method for fabricating an insulated gate control thyristor

1993-10-28

1994-09-13

Thomas, Tom

Fishing, trapping, and vermin destroying

437 6, 437 50, 437152, 437154, H01L 2100

Patent

active

053468384

ABSTRACT:
An insulated gate control thyristor including an n-type base region, an insulating layer, gates formed on the insulating layer, first and second windows formed in the insulating layer, p-type emitter layers and n-type cathode layers diffused into the base region from the first windows, and p-type collector layers diffused into the base region from the second windows. The emitter layer and the collector layer are disposed in close proximity to each other under the gate so that a channel is formed which is conducted when the thyristor is turned off. The turn-off of the thyristor speeds up and becomes reliable, and the quality control of the process steps for fabricating the thyristor becomes easier.

REFERENCES:
patent: 4458408 (1984-07-01), Alonas et al.
patent: 5030581 (1991-07-01), Yakushiji
patent: 5155569 (1992-10-01), Terashima
patent: 5194394 (1993-03-01), Terashima
patent: 5278076 (1994-01-01), Darwish
patent: 5286981 (1994-02-01), Lilja et al.
"The MOS-Gated Emitter Switched Thyristor" B. Jayant Baliga, Electron Device Letters, vol. 11, No. 2 (Feb. 1990), pp. 75-77.
"MOS Control Thyristors (MCT'S)" V. A. K. Temple, IEDM (1984), pp. 282-285.
"The MOS Depletion-Mode Thyristor: A New MOS-Controlled Bipolar Power Device" Baliga et al., IEEE ELECTRON DEVICE LETTERS, vol. 9, No. 8, Aug. 1988, pp. 411-413.

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