Reference for CMOS memory cell having PMOS and NMOS transistors

Details Reference for CMOS memory cell having PMOS and NMOS transistors Reference for CMOS memory cell having PMOS and NMOS transistors

1996-06-21

1998-08-18

Cunningham, Terry

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327543, 327546, 365149, 36518909, G05F 320, G11C 700

Patent

active

057962952

ABSTRACT:
A voltage reference for a CMOS memory cell having PMOS and NMOS transistors with a common floating gate. The reference provides a more stable voltage than voltage supplied from the Vcc pin of a chip. In one embodiment, the reference includes PMOS and NMOS transistors having a common gate and common drains all connected together. A weak current source supplies current to the source of the PMOS transistor of the reference so that voltage at the source of the PMOS transistor of the reference equals the magnitude of the sum of threshold voltages (Vtn+Vtp) of the NMOS and PMOS transistors of the reference. The voltage at the source of the PMOS transistor of the reference is provided as a reference to the source of the PMOS transistor of the CMOS memory cell. The voltage at the drains of the PMOS and NMOS transistors of the reference are provided to a control gate of the CMOS memory cell. To assure zero power operation in subsequent cells following CMOS memory cells utilizing such a reference, cell implants are utilized in the CMOS memory cells and the reference to assure Vtn+Vtp is greater than or equal Vcc, and voltage to the reference is boosted above Vcc.

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"Stabilization of Voltage Limiter Circuit for High-Density DRAMs Using Miller Compensation", Hitoshi Tanaka, Electronics and Communications in Japan, Part 2, Apr. (1993).

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