High-precision voltage dependent timing delay circuit

Details High-precision voltage dependent timing delay circuit High-precision voltage dependent timing delay circuit

1996-12-16

1998-08-18

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327263, H03H 1126

Patent

active

057962847

DESCRIPTION:

BRIEF SUMMARY
The invention concerns a timing delay circuit, particularly for high-speed sensing of signals from a RAM or ROM cell which comprises word lines and bit lines. The invention is further directed to a sensing scheme for memory arrays, in particular to the timing of differential sense amplifiers which sense and amplify signals developed on the respective single bit lines. The proposed circuit and method are particularly relevant to semiconductor memory devices such as dynamic and static random-access memory devices (DRAMs, SRAMs).
High speed random-access memories (RAMS) implemented in complementary metal-oxide semiconductor (CMOS) technology comprise minimum size memory cells which require special circuitry to sense and amplify the small signals delivered by the cells when selected for read operations. Such sense circuits need to be timed precisely so that these signals can be detected reliably. This especially applies for DRAMs using only a one-device cell as storage element, which involves single-ended sensing. But high density multi-port static RAMs (SRAMs) usually permit only single-ended sensing, too, because the memory cell must be minimized with respect to the number of transistors and I/O wiring. For example, a n-port SRAM cell with n data-out ports contains n I/O transistors and n bit lines.
In case of single-ended sensing, each memory cell is connected to a differential sense amplifier via a single bit line (FIG. 6). Hereby the sense amplifier is activated by a `set sense amplifier` (SSA) signal which timing is critical, especially when the supply voltage Vdd of the memory cell is shifted. In conventional, previously known approaches, inverter chains are used to generate the required SSA delay from the leading edge of a SRAM input clock signal.
These circuit schemes are disadvantageous in that said delay varies depending on CMOS process parameters and the applied conditions, like supply voltage and operation temperature. A major problem is that circuit functionality and performance strongly depend on the supply voltage of these circuits.
In particular, it is practically impossible to design these circuits for a wide range of supply voltages, for example from 3.3 to 5.0 V as required for low-power and battery applications, without losing performance at the low-voltage corner. One reason for the considerable loss of performance at high-voltage operations is that at the design point of the sense amplifier chosen to be at Vdd=3.4 V, the sense amplifier transistors and the timing conditions are tuned for maximum performance at this supply voltage, and therefore a change of the supply voltage towards much higher voltages will shift away those conditions from the optimum operating point of the sense amplifier. Thereupon at high voltage conditions, the timing chain runs too fast, and thus the sense amplifier might already be set before a large enough voltage difference has been established.
Furthermore, CMOS product testing requires high-voltage screens and burn-in conditions to ensure reliable circuit operation in the field. For the CMOS4S products recently developed by the present assignee, the challenge is to design a circuit which is fully functional at 5.1 V voltage screen and burn-in conditions, without sacrificing performance at normal system operations where the supply voltage ranges between 3.4 and 3.8 V.
In an article by W. Cordaro, F. D. Jones and R. S. Mao published in the IBM Technical Disclosure Bulletin (TDB), Vol. 26, No. 10B (March 1984), a hardware arrangement to speed up the access time of conventional memory cells comprising word lines and bit lines and a differential sense amplifier is disclosed. particularly described is a delay technique which employs a sense latch triggering circuit with a clock driver comprising a threshold voltage to prevent premature triggering at higher supply voltages.
Further, an article by H. H. Chao and L. M. Terman in IBM TDB, Vol. 25, No. 10 (March 1983), and an article by S. E. Schuster in IBM TDB, Vol. 19, No. 2 (July 1976), are also, more or less, relate

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