Procedure state descriptor system for digital data processors

Details Procedure state descriptor system for digital data processors Procedure state descriptor system for digital data processors

1992-07-30

1995-02-07

Kriess, Kevin A.

Boots, shoes, and leggings

3642646, 3642813, 364DIG1, G06F 300, G06F 922

Patent

active

053882636

ABSTRACT:
A procedure state descriptor system for generating state reports of the progress of the invocation process for procedures executed on a digital data processing system is disclosed. The procedure state descriptor system includes a procedure descriptor generator process that generates a procedure descriptor for each procedure. Each procedure descriptor contains a number of offset values that are offset addresses from the start of the procedure to locations in the procedure that are the demarcations between states of the invocation process for the procedure. When a particular procedure is invoked for execution, a procedure state analyzation process accesses the procedure descriptor offset values for the procedure, the memory address of the start of the procedure, and the address of the next instruction to be executed in the procedure. The procedure state analyzation process then determines the difference between the address of the instruction to be next executed and the starting address of the procedure. The difference between the two addresses is compared to the offset values to determine the state of the invocation process for the procedure. As the result of selected state determinations, the procedure state analyzation process also may review the next instruction to be executed by the invoked procedure. The instruction is reviewed to determine if it is a specific type of instruction indicating that the procedure was in still another invocation state.

REFERENCES:
patent: 4493027 (1985-01-01), Katz et al.
patent: 4649472 (1987-03-01), Kim
Helvig et al., "IBM Technical Disclosure Bulletin-Exception Condition Sequencer," pp. 1627-1634.

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