Transparent data bus sizing

Details Transparent data bus sizing Transparent data bus sizing

1992-10-07

1995-02-07

MacDonald, Allen R.

Boots, shoes, and leggings

364DIG1, 364240, 3642401, 3642403, 3642386, 3642395, 364243, 364260, G06F 1300

Patent

active

053882270

ABSTRACT:
A bus system wherein N-bit devices (12b,12c) attached to the lower half (30L) of a 2N-bit bus (30) communciate with 2N-bit (12a, 12d) devices attached to the full bus. Bi-directional registered transceivers (60,62,65,67) are coupled between the upper and lower halves of the bus. The N-bit devices are capable of asserting a pair of signals called HOLDN and LATCHN. For a 2 N-bit source device transmitting data to an N-bit sink device, the 2 N-bit source puts 2 N bits of data on the upper and lower halves of the bus during a given cycle, during which the N-bit sink device samples the N bits on the lower half of the bus. The assertion of HOLDN causes the N bits on the upper half of the bus to be latched and subsequently driven onto the lower half of the bus. Where an N-bit source device is communicating to a 2 N-bit sink device, the N-bit device puts the high order N bits and low order N bits of data on the lower half of the bus on successive cycles. During the cycle that the high order bits are on the bus, the N bit source device asserts LATCHN which causes the data to be latched and then driven onto the upper half of the bus during the subsequent cycle,

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