Stopclock toggle system for powering two CPUs from a regulator o

Details Stopclock toggle system for powering two CPUs from a regulator o Stopclock toggle system for powering two CPUs from a regulator o

1995-12-15

1997-08-19

Bowler, Alyssa H.

Boots, shoes, and leggings

39518208, 3951822, 395560, 3642283, 3642733, 364DIG1, G06F 110

Patent

active

056597894

ABSTRACT:
The present invention relates to a fault tolerant system for providing power to a multiple central processing unit computer system. Three DC-DC converters, each sized for providing power to one central processing unit, furnish power to two central processing units through two power planes. Each DC-DC converter has an output voltage level selectable through a voltage identification signal. If the voltage identification signals of the converters match, identification logic couples the power planes together. If only one converter is available to power the two central processing units, a stopclock logic circuit alternatively places the central processing units in known stopclock modes. Thus, the single converter only has to fully power one central processing unit at any one time.

REFERENCES:
patent: 4823262 (1989-04-01), Calle
patent: 5465366 (1995-11-01), Heineman
Intel Pentium.RTM. Pro Processor Power Distribution Guidelines, Application Note AP-523, Nov. 1995.

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