Boots – shoes – and leggings
Patent
1994-12-27
1997-08-19
Pan, Daniel H.
Boots, shoes, and leggings
395287, 395296, 395308, 395309, 364DIG1, 364DIG2, G06F 1340, G06F 1342
Patent
active
056597835
ABSTRACT:
An operation unit has operation circuits (aL, aH), temporary registers (xL, yL, xH, yH) arranged just before the operation circuits, registers (R1, R2, R3, R4) arranged if required, and data buses (d1L, d2L, d1H, d2H) for transferring data among the operation circuits, temporary registers, and registers. Data to be processed are divided, are transferred to the operation circuits through the data buses, and are simultaneously and independently processed by the operation circuits. When a result of the preceding operation affects the following operation, data except the result of the preceding operation are transferred from the registers to the temporary registers before starting the operations. These techniques shorten a processing time.
REFERENCES:
patent: 4528641 (1985-07-01), Burrows
patent: 4789957 (1988-12-01), Niehaus et al.
patent: 4811266 (1989-03-01), Woods et al.
patent: 5301340 (1994-04-01), Cook
Patent Abstracts of Japan, vol. 11, No. 107 (P-563)(2554), Apr. 4, 1987, JP-A-61 255433, Nov. 13, 1986.
Hewlett-Packard Journal, vol. 33, No. 3, 1982, Frederic C. Amerson, et al., "High-Performance Computing With Dual ALU Architecture and ECL Logic", pp. 3-11.
Kabushiki Kaisha Toshiba
Pan Daniel H.
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