System and method for handling load and/or store operations in a

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395376, 39580041, 364DIG1, 364DIG2, G06F 938, G06F 940, G06F 930

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active

056597827

ABSTRACT:
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data;

REFERENCES:
patent: 3541528 (1970-11-01), Randell
patent: 4722049 (1988-01-01), Lahti
patent: 4734852 (1988-03-01), Johnson et al.
patent: 4739472 (1988-04-01), Hayashi
patent: 4760519 (1988-07-01), Papworth et al.
patent: 4777592 (1988-10-01), Yano
patent: 4814976 (1989-03-01), Hansen et al.
patent: 5051940 (1991-09-01), Vassiliadis et al.
patent: 5075849 (1991-12-01), Kuriyama et al.
patent: 5133077 (1992-07-01), Karne et al.
patent: 5148536 (1992-09-01), Witek et al.
patent: 5185868 (1993-02-01), Tran
patent: 5251306 (1993-10-01), Tran
patent: 5317740 (1994-05-01), Sites
patent: 5323489 (1994-06-01), Bird
patent: 5487156 (1996-01-01), Popescu et al.
Mike Johnson, "Superscalar Microprocessor Design", Prentice-Hall, Inc. 1991.
J.E. Smith et al., "Implementing Precise Interrupts in Pipelined Processors," IEEE Transactions on Computers, vol. 37, No. 5, May 1988, pp. 562-573.

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