Addressing scheme for accessing a portion of a large memory spac

Details Addressing scheme for accessing a portion of a large memory spac Addressing scheme for accessing a portion of a large memory spac

1992-01-10

1995-01-31

Harvey, Jack B.

Boots, shoes, and leggings

364DIG1, 364245, 3642472, 364254, 3642543, 3642551, 3642558, 364259, 3642591, G06F 1200, G06F 1206

Patent

active

053865235

ABSTRACT:
A method for generating an address for addressable locations of a computer system where two registers are overlapped. Those bits of the two registers that overlap are logically combined together using a boolean operation when generating the address. Using this method, the higher order register can be used to select a segment of the addressable space of the computer system. Then, all accesses to that portion of the addressable space can be controlled by changing only the lower order register. This results in a saving of time since only one of the registers need be reloaded for each subsequent access.

REFERENCES:
patent: 4831522 (1989-05-01), Henderson et al.
patent: 5093783 (1992-03-01), Kitada
patent: 5109334 (1992-04-01), Kamuro
patent: 5150471 (1992-09-01), Tipon
patent: 5210839 (1993-05-01), Powell et al.

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