Patent
1986-06-06
1988-11-15
Larkins, William D.
357 52, 357 231, 357 238, 357 2311, 357 2314, H01L 2978, H01L 2940
Patent
active
047853433
ABSTRACT:
The present invention relates to a MIS FET having an additional gate electrode (referred to as a suppression gate electrode) which extends along a boundary region between a MIS FET active region and a field oxide film under a drain wiring. When the drain wiring is supplied with a voltage high enough to induce an inversion layer of the same polarity as the MIS FET channel, a parasitic transistor is formed in parallel with the MIS FET and creates an increase in leakage current. A suppression gate electrode of the present invention forms an interrupting transistor connected in series with the parasitic transistor and therefore cuts off the leakage current.
Fujitsu Limited
Jackson Jerome
Larkins William D.
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