High speed NOR gate

Details High speed NOR gate High speed NOR gate

1985-11-14

1987-02-24

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307451, 307468, 307469, H03K 1901, H03K 19013

Patent

active

046459529

ABSTRACT:
A high speed CMOS NOR gate employs a pair of cross-coupled inverters and a dual set of N-channel pulldown transistors (202, 203) at each of the nodes between the two inverters, together with small pullup transistor (205) on the output terminal that is permanently energized and a switchable large pullup transistor (220) that is a link between the second inverter output and the first inverter input.

REFERENCES:
I.B.M. Technical Disc. Bul. vol. 19, No. 7, Dec. 1976, p. 2632, "Optimized Gate Size for FET Random Logic".

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